1. Field of the Invention
The present invention relates to a capacitor in a dynamic random access memory (DRAM), and more particularly, to a structure of a lower electrode of a capacitor which inhibits occurrence of bridges between nodes, and to a method for fabricating the same.
2. Background of the Related Art
As a semiconductor memories have developed from millions of transistors on a single chip to billions of transistors on a single chip, a number of methods have been employed to increase an effective area of a capacitor within a restricted area of a cell in the semiconductor memory. For example, the effective area of the capacitor is increased by forming a three dimensional storage node, such as a trench type or a cylinder type. Further, a surface of a storage electrode used as a lower electrode of the capacitor is formed of HSG-Si (Hemispherical Grain-Silicon) that has a rough morphology rather than a smooth morphology, thereby increasing the effective area of the capacitor. Moreover, the three dimensional storage node approach and the HSG-Si approach can be combined.
The combined approach to increase the effective area of the capacitor will now be explained with reference to FIGS. 1A-1D. FIGS. 1A-1D illustrate cross-sections each showing a lower electrode of a capacitor (of a cylinder type) with an HSG-Si applied to it.
Referring to FIG. 1A, an interlayer insulating film 3 is deposited on a semiconductor substrate 1 having an impurity region 2 formed therein. Then, a portion of the interlayer insulating film 3 over the impurity region 2 is selectively removed, to form a contact hole for a capacitor storage electrode. Next, an amorphous silicon layer 4 is deposited. Preferably, the amorphous silicon layer 4 is formed of an amorphous silicon doped with phosphorus at a concentration of approximately 2.0.times.10.sup.20 atoms/cm.sup.3.
As shown in FIG. 1B, an oxide film 5 is deposited on an entire surface of the device, and photoetched to selectively remove portions of the oxide film 5, leaving the patterned oxide film 5 in a region around the contact hole. Then, the patterned oxide film 5 is used as a mask to selectively remove the amorphous silicon layer 4. An amorphous silicon layer is deposited on an entire surface of the device and anisotropically etched to form amorphous silicon sidewalls 6 at sides of the patterned oxide film 5. The amorphous silicon sidewalls 6 and the amorphous silicon layer 4 are electrically connected.
As shown in FIG. 1C, all of the oxide film 5 is removed, thereby forming lower electrode 7 of a cylindrical capacitor. As shown in FIG. 1D, silicon seeds are formed on a surface of the lower electrode 7 using a seeding gas (such as Si.sub.2 H.sub.6 or SiH.sub.4) at approximately 570-620.degree. C. in an HSG-Si forming apparatus, and then annealed, to form an HSG-Si layer 8 with a rough surface. Thus, a cylindrical lower electrode 7 with an HSG-Si "mushroom" structure can be formed. Though not shown in these figures, by forming a dielectric film and an upper electrode in succession on the cylindrical lower electrode 7, the capacitor is completed.
However, the capacitor and the method for fabricating the capacitor for a DRAM as described above has a number of problems. For example, with a gap below 0.2 .mu.m between storage nodes of capacitors in the semiconductor memory with a high device packing density, and with the HSG-Si formed on a three dimensional structure like the cylindrical structure, the HSG-Si can fall off from regions with lower adhesive forces and subsequently remain between the storage nodes, without being removed even by a cleaning process. Thus, the HSG-Si can create bridges that cause electrical shorts between the nodes, mostly by the HSG-Si that has fallen off from peak points (end points in the cylindrical form) in the lower electrode. That is, the weak connection of a neck portion of the HSG-Si "mushroom" structure (resulting from a lack of the amorphous silicon required for formation of the HSG-Si due to a relatively thin amorphous silicon at the peak point) causes the fall-off or hang-down that formed bridges between adjacent nodes. Also, the HSG-Si connected to an external surface of the lower electrode can fall-off or hang-down in the course of cleaning or a high temperature annealing process, thereby causing bridges between adjacent nodes.